The present invention relates to a system and method for the patching of programmable memory.
It is often desirable to be able to patch the contents of program memory after a device has been manufactured. For example, there may be a requirement to deploy an upgrade to software. Where devices utilise Random Access Memory (RAM), Flash, or other multiple-write types of memory such patches are straightforward as the existing content can simply be overwritten. However, in some types of device patching is more difficult.
One type of memory for which patching is more difficult is One Time Programmable (OTP) memory. OTP memory is computer memory that can be programmed only once. For example, in so-called anti-fuse memory at manufacture the unprogrammed state of each bit is ‘0’ and it is possible to program each bit to a ‘1’ such that the memory contains the required data. Once a bit has been changed to a ‘1’ no further changes are possible to this bit. Another example of OTP is a write-once CD-ROM. A known technique for patching OTP memory is the inclusion of a comparator to compare an address requested by a processor utilising the memory with an address where a patch is required. If the comparator identifies a request for a patched address a multiplexor on the memory output is controlled to output the patched content rather than the original memory content. However, this system requires additional components for the comparator and multiplexor, with typically one comparator being required for each patched address. The use of this technique therefore adds complexity and cost to devices and can also require additional power to implement. The number of addresses that can be patched is also limited by the comparator and multiplexor configuration.
Another technique that has been used is to place a cache in front of the OTP memory and then lock patch code into cache lines. When the processor fetches data from the OTP memory address, the cache will instead provide the data from the locked cache lines. This scheme has a disadvantage of requiring a cache, which can add a significant amount of additional logic and power consumption if it must be provided especially for patching purposes.
There is therefore a requirement for an improved method and system for patching programmable memory.